* TEST PROGRAM FOR X16 -- VERSION 2
* X16 IS AN FPGA IMPLEMENTATION OF THE HONEYWELL 316/516
* THIS PROGRAM CHECKS ALL THE CPU INSTRUCTIONS, NOT IN DEPTH, BUT AS A QUICK
* CHECK. IT ALSO CHECKS THE MEMORY (16K WORDS), THE ADDRESSING MODES, INTERRUPT
* MECHANISM AND THE RTC AS WELL AND TTY INPUT AND OUTPUT.
*
* START ADDRESS: (OCTAL) 1000
*
* DATE: JAN-10-2010
*
* AUTHOR : THEO ENGEL
* CONTACT: INFO@THEOENGEL.NL
*
\LOAD
\ORG\'100
\BCI\8,X16 TEST PROGRAM
M1\EQU\*
\BCI\9,RAM TEST; #SWEEPS:
M2\EQU\*
M8\DEC\-8
M9\DEC\-9
O260\OCT\'260\ASCII 0
SWP\DEC\0
SSWP\DEC\0
ONL\OCT\'106612\NLCR
ONE\DEC\1
FFFF\OCT\'177777
F00F\OCT\'170017
FF00\OCT\'177400
FF\OCT\'000377
FF0F\OCT\'177417
F0FF\OCT\'170377
MSB\OCT\'100000
LN\OCT\'77777
NULL\DEC\0
SAVE\DEC\0
MPAG\OCT\'777
MSEC\OCT\'177000
PNTR\DEC\0
MEND\OCT\'27777\12K
M10\BCI\1,RY
\BCI\1,01
\BCI\1,02
\BCI\1,03
\BCI\1,04
\BCI\1,05
\BCI\1,06
\BCI\1,07
\BCI\1,08
\BCI\1,09
\BCI\1,10
* PAGE TABLE (PREINDEXING)
P\EQU\*
P2\DAC\'2000
P3\DAC\'3000
P4\DAC\'4000
P5\DAC\'5000
P6\DAC\'6000
P7\DAC\'7000
* PAGE TABLE (POSTINDEXING)
PP\EQU\*
PP2\DAC\'12000,1
PP3\DAC\'13000,1
PP4\DAC\'14000,1
PP5\DAC\'15000,1
PP6\DAC\'16000,1
PP7\DAC\'17000,1
*
A\DAC\AA
B\DAC\BB
C\DAC\CC
D\DAC\DD
E\DAC\EE
F\DAC\FFF
G\DAC\GG
H\DAC\HH
A11\OCT\'177777
B11\OCT\'177400
C11\OCT\'377
D11\OCT\'100001
E11\OCT\'000600
F11\OCT\'000400
G11\OCT\'000200
*
TMII\DAC\TMI\MULTILEVEL INDIRECTS
SHII\DAC\SHFT\SHIFT INSTRUCTION ROUTINES
MTST\DAC\MEMT\TEST\MEMORY TEST ROUTINE
TRTC\DAC\TINT\TEST INTERRUPT ROUTINE
*
* PRINT ASCII
ASRO\DAC\**
\SKS\'104
\JMP\*-1
\OCP\'104
\OTA\4
\JMP\*-1
\JMP*\ASRO
*
* READ ASCII
ASRI\DAC\**
\SKS\'104
\JMP\*-1
\OCP\'4
\INA\'1004
\JMP\*-1
\JMP*\ASRI
*
* PRINT 2 ASCII'S
PRIN\DAC\**
\ICA
\JST\ASRO
\ICA
\JST\ASRO
\JMP*\PRIN
*
* PRINT NLCR
NLCR\DAC\**
\LDA\ONL
\JST\PRIN
\JMP*\NLCR
*
\ORG\'1000
STRT\LDX\M8\START ADDRESS
\LDA\M1,1
\JST\PRIN
\IRS\0
\JMP\*-3
\JST\NLCR
* SETUP THE MEMORY TEST
\LDX\M9
\LDA\M2,1
\JST\PRIN
\IRS\0
\JMP\*-3
\JST\ASRI\NUMBER OF SWEEPS?
\SUB\O260
\STA\SWP
*
STT\EQU\*\TEST LOOP (TEST 1--10)
\JST\NLCR
*
* TEST 1
*
\SR1
\HLT
\SR2
\HLT
\SR3
\HLT
\SR4
\HLT
\SSR
\HLT
\SS1
\SR1
\HLT
\SS2
\SR2
\HLT
\SS3
\SR3
\HLT
\SS4
\SR4
\HLT
\SSS
\SSR
\HLT
\LDA*\A
\STA*\B
\ERA*\A
\STA*\C
\SZE
\HLT
\LDA*\A
\ANA*\E
\SUB*\E
\SZE
\HLT
\IMA*\B
\ERA*\A
\SZE
\HLT
\JST*\F
\SNZ
\SKP
\JMP\*-3
\CAS*\G\A=0
\HLT\\>
\HLT\\=
\LDA*\G
\CAS*\G
\HLT\\>
\SKP\\=
\HLT\\<
\LDA*\A
\SSP
\CAS*\G\A='77777
\NOP\\>
\SKP\\=
\HLT\\<
\ANA*\D\A='77770=> '77770
\CMA\\A='100007
\ERA*\H
\SZE
\HLT
\LDA*\A
\STA*\B
\IRS*\B
\HLT
\LDX*\D
\STX*\B
\LDA*\B
\ERA\0
\SZE
\HLT
*
\CRA
\CMA\
\ERA\A11
\SZE
\HLT
\SCB\\C=1
\SSC
\HLT
\ACA\\A=1
\SLN
\HLT
\CMA\\A=177776
\SLZ
\HLT
\CSA\\C=1 A=77776
\SSC
\HLT
\SPL
\HLT
\CHS\\A=177776
\SMI
\HLT
\SNZ
\HLT
\CHS\\A=77776
\SSM\\A=177776
\SMI
\HLT
\CAR\\A=177400
\ERA\B11
\SZE
\HLT
\LDA\A11
\CAL\\A=377
\ERA\C11
\SZE
\HLT
\TCA
\SZE
\HLT
\SSC
\HLT
\LDA\D11
\ICA
\SUB\E11
\SZE
\HLT
\LDA\D11
\ICR\\A=000400
\ERA\F11
\SZE
\HLT
\LDA\D11
\ICL\\A=000200
\ERA\G11
\SZE
\HLT
\LDA\A11
\IAB
\CRA
\IAB
\CMA
\SZE
\HLT
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+1
\JST\PRIN
*
* TEST 2 (INDEXING)
*
* PREINDEXING
* CLEAR MEMORY
\LDA\P2
\STA\SAVE
\CRA
CM1\STA*\SAVE
\IRS\SAVE
\LDA\SAVE
\CAS\A11
\JMP\*+3\>
\JMP\CM1\=
\JMP\CM1\<
*
\CRA
\STA\0\X=0
\LDA\P2
\STA\SAVE
MM1\CRA
\CMA
\STA*\P,1
\IRS\P2
\LDA\P2
\CAS\P3
\HLT
\SKP
\JMP\MM1
\LDA\SAVE
\STA\P2
MM2\IRS*\P,1
\HLT
\IRS\P2
\LDA\P2
\CAS\P3
\HLT
\SKP
\JMP\MM2
\LDA\SAVE
\STA\P2
* SAME WITH P3
* CLEAR MEMORY
\CRA
CM2\STA*\SAVE
\IRS\SAVE
\LDA\SAVE
\CAS\A11
\JMP\*+3\>
\JMP\CM2\=
\JMP\CM2\<
*
\IRS\0
\LDA\P3
\STA\SAVE
MM3\CRA
\CMA
\STA*\P,1
\IRS\P3
\LDA\P3
\CAS\P4
\HLT
\SKP
\JMP\MM3
\LDA\SAVE
\STA\P3
MM4\IRS*\P,1
\HLT
\IRS\P3
\LDA\P3
\CAS\P4
\HLT
\SKP
\JMP\MM4
\LDA\SAVE
\STA\P3
* POSTINDEXING
\CRA
\STA\0
MM5\CRA
\CMA
\STA*\PP2
\IRS\0
\LDA\0
\CAS\MPAG
\JMP\*+3
\NOP
\JMP\MM5
\CRA\\CHECK
\STA\0
MM6\IRS*\PP2
\HLT
\IRS\0
\LDA\0
\CAS\MPAG
\JMP\*+3
\NOP
\JMP\MM6
* SAME WITH P7
\CRA
\STA\0
MM7\CRA
\CMA
\STA*\PP7
\IRS\0
\LDA\0
\CAS\MPAG
\JMP\*+3
\NOP
\JMP\MM7
\CRA\\CHECK
\STA\0
MM8\IRS*\PP7
\HLT
\IRS\0
\LDA\0
\CAS\MPAG
\JMP\*+3
\NOP
\JMP\MM8
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+2
\JST\PRIN
*
* TEST 3 (IMA)
*
\LDA\P7
\STA\PNTR
\LDA\MPAG
\TCA
\STA\0
MM9\CRA
\IMA*\PNTR
\IRS\PNTR
\IRS\0
\JMP\MM9
\LDA\P7
\STA\PNTR
\LDA\MPAG
\TCA
\STA\0
MM10\IMA*\PNTR
\SZE
\HLT
\IRS\PNTR
\IRS\0
\JMP\MM10
\LDA\P7
\STA\PNTR
\LDA\MPAG
\TCA
\STA\0
MM11\CRA
\CMA
\IMA*\PNTR
\IRS\PNTR
\IRS\0
\JMP\MM11
\LDA\P7
\STA\PNTR
\LDA\MPAG
\TCA
\STA\0
MM12\IMA*\PNTR
\AOA
\SZE
\HLT
\IRS\PNTR
\IRS\0
\JMP\MM12
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+3
\JST\PRIN
*
* TEST 4 (ICA, ETC.)
*
\CRA
\CMA
\IAB
\CRA
\IAB
\CAR
\ERA\FF00
\SZE
\HLT
\CMA
\CAL
\ERA\FF
\SZE
\HLT
\LDA\F00F
\ICA
\ANA\F00F
\SZE
\HLT
\LDA\F00F
\ICR
\ERA\F0FF
\ERA\FFFF
\SZE
\HLT
\LDA\F00F
\ICL
\ERA\FF0F
\ERA\FFFF
\SZE
\HLT
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+4
\JST\PRIN
*
* TEST 5
*
\LDX\M9
\STX\SAVE
\LDA\M9
\TCA
\ADD\SAVE
\SZE
\HLT
MM13\SCB
\SSC
\HLT
\LDA\FFFF
\SSC
\HLT
\AOA
\SRC
\HLT
\SZE
\HLT
\CMA
\SMI
\HLT
\SLN
\HLT
\SCB
\ACA
\SZE
\HLT
\SPL
\HLT
\SLZ
\HLT
\CHS
\SMI
\HLT
\RCB
\SRC
\HLT
\LDA\FFFF
\CSA
\SPL
\HLT
\SSC
\HLT
\CMA
\SMI
\HLT
\AOA
\SRC
\HLT
\SUB\ONE
\SRC
\HLT
\SUB\ONE
\SSC
\HLT
\RCB
\LDA\LN
\SRC
\HLT
\AOA
\SSC
\HLT
\CRA
\CAS\NULL
\HLT
\SKP
\HLT
\CAS\FFFF
\JMP\*+3
\HLT
\HLT
\CAS\ONE
\HLT
\HLT
\LDA\MSB
\AOA
\CAS\MSB
\JMP\*+3
\HLT
\HLT
\LDA\LN
\CAS\MSB
\JMP\*+3
\HLT
\HLT
\LDA\MSB
\CAS\LN
\HLT
\HLT
\IRS\SAVE
\JMP\MM13
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+5
\JST\PRIN
*
* TEST 6
*
\CRA
\AOA
\SNZ
\HLT
\LDA\LN
\ADD\ONE\OVERFLOW
\SNZ
\HLT
\SMI
\HLT
\SSC
\HLT
\LDA\LN
\ACA\\OVERFLOW
\SNZ
\HLT
\SMI
\HLT
\SSC
\HLT
\CRA
\ACA
\SUB\ONE
\SZE
\HLT
\SRC
\HLT
\RCB
\LDA\MSB
\SUB\ONE\OVERFLOW
\SSC
\HLT
\RCB
\SUB\LN
\SZE
\HLT
\SRC
\HLT
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+6
\JST\PRIN
*
* TEST 7 MULTI LEVEL INDIRECT ADDRESSING
*
\JST*\TMII
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+7
\JST\PRIN
*
* TEST 8 SHIFT INSTRUCTIONS
*
\JST*\SHII
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+8
\JST\PRIN
*
* TEST 9: MEMORY TEST
*
\JST*\MTST
* READY
\LDA\M10
\JST\PRIN
\LDA\M10+9
\JST\PRIN
*
* TEST 10: INTERRUPT AND RTC
*
T10\JST*\TRTC
*
*   RESTART
*
RST\JMP\STT\RESTART
*******************************************************************
*
* START OF MEM TO TEST AREA
*
PPP1\DAC\*+1
* END OF MEMORY TEST AREA
\ORG\'30000
*
* MEMORY TEST ROUTINE
*
MEMT\DAC\**
\LDA\SWP
\STA\SSWP
ST\JST\ONCE
\LDA\FFFF
\JST\ONCE
\LDA\MSB
\JST\ONCE
\CRA\\TEST ZERO
\JST\ONCE
\LDA\SSWP
\SUB\ONE
\STA\SSWP
\SZE
\JMP\ST
\JMP*\MEMT
*
* ROUTINE TO FILL MEMORY
*
ONCE\DAC\**
\STA\SAVE
\LDA*\PP1
\STA\PNTR
H1\LDA\SAVE
\STA*\PNTR
\IRS\PNTR
\LDA\PNTR
\CAS\MEND
\HLT
\SKP\\END MEMORY
\JMP\H1
* COMPARE STORED VALUES
\LDA*\PP1
\STA\PNTR
H2\LDA*\PNTR
\CAS\SAVE
\HLT
\SKP\\EQUAL
\HLT
\ANA\SAVE
\ERA\SAVE\SHOULD BE 0
\SZE
\HLT
\LDA\SAVE
\CMA
\ANA*\PNTR\SHOULD BE 0
\SZE
\HLT
\LDA\SAVE
\ERA*\PNTR\PNTR\SHOULD BE 0
\SZE
\HLT
\IRS\PNTR
\LDA\PNTR
\CAS\MEND
\HLT
\SKP
\JMP\H2
\JMP*\ONCE\READY
PP1\DAC\PPP1
*
* TEST MULTI LEVEL INDIRECT
TMI\DAC\**
\CRA
\STA\0
\LDA*\TBA1
\CAS\ONE
\HLT
\SKP
\HLT
\ERA*\TBA1
\SZE
\HLT
\AOA
\STA\0
\LDA*\TBA1
\CAS\MSB
\HLT
\SKP
\HLT
\ERA*\TBA1
\SZE
\HLT
\STA\0
\LDA*\TBA1,1
\CAS\ONE
\HLT
\SKP
\HLT
\ERA*\TBA1,1
\SZE
\HLT
\AOA
\STA\0
\LDA*\TBA1,1
\CAS\MSB
\HLT
\SKP
\HLT
\ERA*\TBA1,1
\SZE
\HLT
\JMP*\TMI
TBA1\DAC*\*+2
TBA2\DAC*\*+1
\DAC*\*+1
\DAC*\*+1
\DAC*\*+1
\DAC*\*+1
\DAC\*+1,1
\DEC\1
\OCT\'100000
*
* TEST SHIFT INSTRUCTIONS
*
SHFT\DAC\**
* LONG SHIFTS
\CRA
\RCB\\C=0
\AOA\\A16=1
\IAB\\A=0, B16=1
\LLL\32
\SZE\\? A=0
\HLT
\SSC\\? C=1
\HLT
\RCB
\IAB
\SZE\\? B=0
\HLT
*
\LDA\MSB\A1=1, B=0
\LRL\32
\SZE\\? A=0
\HLT
\IAB\\? B=0
\SZE
\HLT
\SSC\\? C=1
\HLT
*
\RCB\\C=0
\AOA\\A16=1, B=0
\LLR\16
\SSC\\? C=0
\HLT
\SZE\\? A=0
\HLT
\IAB\\? B16=1
\SLN
\HLT
*
\RCB\\C=0 A16=1 B=0
\LRR\16
\SRC\\? C=0
\HLT
\SZE\\? A=0
\HLT
\IAB\\? B16=1
\SLN
\HLT
\IAB
\LRR\1
\CAS\MSB\? A1=1
\HLT
\SKP
\HLT
\SSC\\? C=1
\HLT
\IAB\\? B=0
\SZE
\HLT
*
\RCB
\CRA
\CMA\\B=FFFF
\IAB
\LLS\31
\SZE\\? A=0
\HLT
\IAB\\? B=8000
\CAS\MSB
\HLT
\SKP
\HLT
\SSC\\? C=1
\HLT
*
\RCB\\C=0
\CRA\\
\IAB\\B=0
\CRA\\A=0
\CMA\\A=FFFF
\LRS\31
\ERA\FFFF\? A=FFFF
\SZE
\HLT
\SSC\\? C=1
\HLT
\IAB\\? B=7FFF
\CMA
\CAS\MSB
\HLT
\SKP
\HLT
*
* SHORT SHIFTS
\RCB\\LGL
\CRA
\AOA
\LGL\15
\SMI\\A1=1?
\HLT
\LGL\1
\SSC\\C=1?
\HLT
\SZE\\A=0?
\HLT
\RCB
\CMA
\LGL\16
\SSC\\C=1?
\HLT
\SZE\\A=0?
\HLT
*
\RCB\\LGR
\CHS\\A1=1
\LGR\15
\SLN\\A16=1?
\HLT
\LGR\1
\SZE\\A=0?
\HLT
\SSC\\C=1?
\HLT
\RCB
\CMA
\LGR\16
\SZE\\A=0?
\HLT
\SSC\\C=1?
\HLT
*
\RCB\\ALR
\CRA
\AOA
\ALR\15
\SRC\\C=0?
\HLT
\ALR\1
\SPL\\A1=0?
\HLT
\SSC\\C=1?
\HLT
\SLN\\A16=1?
\HLT
\RCB
\LGR\1
\SZE\\A=0?
\HLT
\SSC\\C=1?
\HLT
*
\RCB\\ARR
\AOA
\ARR\1
\SLZ\\A16=0?
\HLT
\SSC\\C=1?
\HLT
\SMI
\HLT\\A1=1?
\RCB
\ARR\15
\SLN\\A16=1?
\HLT
\LGR\1
\SZE\\A=0?
\HLT
\SSC\\C=1?
\HLT
*
\RCB\\ALS
\AOA
\ALS\15
\SMI\\A1=1?
\HLT
\SSC\\C=1?
\HLT
\RCB
\ALS\1
\SZE\\A=0?
\HLT
\SSC\\C=1?
\HLT
\ALS\1
\SRC\\C=0?
\HLT
*
\LDA\MSB\ARS
\ARS\15
\SRC\\C=0?
\HLT
\CMA
\SZE\\A=0?
\HLT
\AOA
\ARR\2
\ARS\15
\SZE\\A=0?
\HLT
\SSC\\C=1?
\HLT
*
\JMP*\SHFT
*
AA\OCT\'177777
BB\DEC\0
CC\DEC\0
DD\OCT\'177770
EE\DEC\7
*
FFF\DAC\**
\AOA
\JMP*\*-2
*
GG\OCT\'1000
HH\OCT\'100007
*
* ROUTINE TO TEST INTERRUPT LOGIC AND RTC
*
TINT\DAC\**
\LDA\N10
\STA\CNT\CHECK 10 CLOCK INTERRUPTS
\LDA\M50
\STA\RTC\INIT RTC TO INTERRUPT (1 SEC)
\OCP\'20\START RTC
*
*    INIT THE INTERRUPT PROCESSING
\LDA\LINK
\STA\INT
\LDA\MASK\ENABLE RTC INTERRUPT
\SMK\'20
\ENB
\JMP\*\AND WAIT FOR AN INTERRUPT
LINK\DAC\*+1
*
*
*    INTERRUPT ROUTINE, ENTERS HERE
IPRC\***\**
*    CHECK FOR A CLOCK INTERRUPT
\SKS\'20
\JMP\CLCK
*    NO RTC INTERRUPT, SO ERROR
\HLT
\JMP\*-1
*
*    RTC INTERRUPT
CLCK\STA\SA
\LDA\AST\PRINT A *
\SKS\'104
\JMP\*-1
\OCP\'104
\OTA\4
\JMP\*-1
\DXA
\IRS\CNT
\SKP\\NO 10 INTERRUPTS YET
\JMP*\TINT\STOP
* RELOAD THE RTC LOCATION AND ENABLE INTERRUPT AND BACK TO PROGRAM
\LDA\M50
\STA\RTC\   
\OCP\'20\RESET CLOCK INTERRUPT
\LDA\SA\RESTORE A
\ENB\
\JMP*\IPRC\
*
RTC\EQU\'61\CLOCK LOCATION
INT\EQU\'63\INTERRUPT LOCATION
MASK\DEC\1\RTC MASK BIT
AST\BCI\1, *
SA\DEC\0\LOCATION TO SAVE A REG
M50\DEC\-50\50 TICK PER SECOND
N10\DEC\-10\10 CLOCK INTERRUPTS
CNT\DEC\0\INTERRUPT COUNTER
\END